A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

被引：12

作者：

Brandon, Tyler L. ^{[1
]}

Koob, John C. ^{[1
]}

van den Berg, Leendert ^{[2
]}

Chen, Zhengang ^{[4
]}

Alimohammad, Amirhossein ^{[2
]}

Swamy, Ramkrishna ^{[3
]}

Klaus, Jason ^{[5
]}

Bates, Stephen ^{[4
]}

Gaudet, Vincent C. ^{[1
]}

Cockburn, Bruce F. ^{[1
]}

Elliott, Duncan G. ^{[1
]}

机构：

[1] Univ Alberta, Dept Elect & Comp Engn, Edmonton, AB T6G 2V4, Canada

[2] Ukalta Engn Corp, Edmonton, AB T5J 4P6, Canada

[3] Aptina Imaging Inc, San Jose, CA 95134 USA

[4] Raithlin Semicond Inc, Canmore, AB T1W 1A1, Canada

[5] Google Inc, San Jose, CA 94043 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2009年 / 56卷 / 05期

关键词：

CMOS integrated circuits; convolutional codes; forward error correction; iterative decoding; low-density parity-check (LDPC) codes; DENSITY; ARCHITECTURE; DESIGN;

D O I：

10.1109/TCSI.2009.2016592

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We present a rate-1/2 (128,3,6) LDPC convolutional code encoder and decoder that we implemented in a 90-mn CMOS process. The 1.1-Gb/s encoder is a compact, low-power implementation that includes one-hot encoding for phase generation and built-in termination. The decoder design uses a memory-based interface with a minimum number of memory banks to deliver an information throughput of 1 b per clock cycle. The decoder shares one controller among a pipeline of decoder processors. The decoder dissipates 0.61 nJ of energy per decoded information bit at an SNR of 2 dB and a decoded throughput of 600 Mb/s. On-chip test circuitry permits accurate power measurements to be made at selectable SNR settings.

引用

页码：1017 / 1029

页数：13

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