The front-end electronics for the HADES RPC wall (ESTRELA-FEE)

被引：19
作者：
Belver, D. [1 ]
Garzon, J. A.
Gil, A.
Gonzalez-Diaz, D.
Koenig, W.
Lange, S.
Marin, J.
Montes, N.
Skott, P.
Traxler, M.
Zapata, M.
机构：
[1] Univ Santiago de Compostela, Dept Fis Particulas, LabCAF, Santiago De Compostela 15782, Spain
[2] IFIC, Inst Fis Corpuscular, Valencia 46071, Spain
[3] GSI Darmstadt, D-64291 Darmstadt, Germany
[4] CIEMAT, E-28040 Madrid, Spain
来源：
NUCLEAR PHYSICS B-PROCEEDINGS SUPPLEMENTS | 2006年 / 158卷
关键词：
D O I：
10.1016/j.nuclphysbps.2006.07.032
中图分类号：
O412 [相对论、场论]; O572.2 [粒子物理学];
学科分类号：
摘要：
A new front-end electronics (FEE) system for RPC timing measurements has been developed for the ESTRELA project, which is part of the upgrade of the HADES experiment at GSI. The RPCs will cover an area of 8 m(2) with 2048 electronic channels. The chain consists on 2 boards: a 4-channel daughterboard (DB) and a 32-channel motherboard (MB). The DB uses a fast 2 GHz amplifier that feeds a discriminator with a constant threshold and an operational amplifier for a charge measurement by a Time-Over-Threshold (ToT) method for the integrated signal (for a slewing correction). The MB is connected to 8 DB, and provides voltage regulation, DACs for signal thresholds and a trigger logic. The MB delivers the differential output signals to an external HPTDC chip. Results are presented for (a) narrow electronic test pulses and for (b) RPC signals from gamma photons, showing a timing jitter around 15 ps/channel (for pulses above 100 fC) and 30-40 ps/channel, respectively. Tests with coincidently firing channels reveal levels of cross-talk below a 1% for a threshold of 25 fC, with a degradation of the time resolution of 10 ps at most.
引用
收藏
页码：47 / 51
页数：5
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