Design of an Efficient Power Delivery Network in an SoC to Enable Dynamic Power Management

被引：0

作者：

Amelifard, Behnam ^{[1
]}

Pedram, Massould ^{[1
]}

机构：

[1] Univ So Calif, Dept EE Syst, Los Angeles, CA 90089 USA

来源：

ISLPED'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN | 2007年

关键词：

Low-power design; power delivery network; DC-DC converter; voltage regulator;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Dynamic voltage scaling (DVS) is known to be one of the most efficient techniques for power reduction of integrated circuits. Efficient low voltage DC-DC conversion is a key enabler for the design of any DVS technique. In this paper we show how to design an efficient power delivery network for a complex system-on-a-chip (SoC) so as to enable dynamic power management through assignment of appropriate voltage level (and the corresponding clock frequency) to each function block in the SoC. We show that the proposed technique reduces the power loss of the power delivery network by an average of 34% while reducing its cost by an average of 8%.

引用

页码：328 / 333

页数：6