A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension

被引:43
作者
Jie, Lu [1 ]
Zheng, Boyi [1 ]
Chen, Hsiang-Wen [1 ]
Flynn, Michael P. [1 ]
机构
[1] Univ Michigan, Elect Engn & Comp Sci EECS Dept, Ann Arbor, MI 48109 USA
关键词
ADC; cascade form; discrete-time (DT) amplifier; noise shaping (NS); successive approximation (SAR); MODULATOR;
D O I
10.1109/JSSC.2020.3019487
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The emerging noise-shaping (NS) successive approximation (SAR) architecture is highly efficient and compact; however, the order and signal-to-noise ratio (SNR) of sub-MHz NS SAR ADCs are still lower than conventional sigma-delta ADCs. This work proposes a cascaded NS ( CaNS) SAR architecture that increases system order and enables more effective NS for higher SNR. The proposed architecture enhances the robustness of high-order NS performance at the system level and is inherently process, voltage and temperature (PVT) stable. A two-phase settling technique improves the efficiency of residue amplification without sacrificing robustness. A prototype CaNS SAR ADC, fabricated in 28-nm CMOS, occupies 0.02 mm(2) and consumes 120 mu W. The measured Signal to Noise and Distortion Ratio (SNDR) over 100-kHz bandwidth is 88 dB, resulting in a Schreier Figure of Merit (FoM) of 177 dB.
引用
收藏
页码:3236 / 3247
页数:12
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