Hadoop Cluster with FPGA-based Hardware Accelerators for K-means Clustering Algorithm

被引：0

作者：

Chung, Ching-Che ^{[1
]}

Wang, Yu-Hsin ^{[1
]}

机构：

[1] Natl Chung Cheng Univ, Dept CSIE, Chiayi, Taiwan

来源：

2017 IEEE INTERNATIONAL CONFERENCE ON CONSUMER ELECTRONICS - TAIWAN (ICCE-TW) | 2017年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the implementation of the K-means clustering algorithm on a Hadoop cluster with FPGA-based hardware accelerators is presented. The proposed design follows MapReduce programming model and uses Hadoop distribution file system (HDFS) for storing large dataset. The proposed FPGA-based hardware accelerator for speed up the K-means clustering algorithm is implemented on Xilinx VC707 evaluation boards (EVBs). There are four computers in the proposed Hadoop cluster, one computer is Master Node, and the other three computers are Slave Nodes. The Slave Nodes communicate with VC707 EVBs through Gigabit Ethernet. The experimental results show that for clustering 125 million three-dimensional input dataset, the proposed design can achieve 4x speedup than the Hadoop cluster without FPGA-based hardware accelerators.

引用

页数：2