Scaleable check node centric architecture for LDPC decoder

被引:0
作者
Singhal, R [1 ]
Choi, GS [1 ]
Mickler, N [1 ]
Koteeswaran, P [1 ]
机构
[1] Texas A&M Univ, College Stn, TX 77840 USA
来源
2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 4, PROCEEDINGS | 2004年
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Low density parity check codes are a popular class of linear block codes for forward error correction in communication channels. Recent years have seen a lot of work towards the development of decoding architectures for these codes. The architectures range from completely parallel to completely serial. While the parallel architectures have a high throughput, they have a large hardware resource requirement. On the other hand, although the serial architectures are very efficient in terms of hardware requirement, they suffer from low throughput. This paper presents a novel scalable check node centric architecture with a 1.5Gbps throughput. The throughput may be further increased by using more readily scalable data-paths which have a individual throughput of 0.5Gbps.
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收藏
页码:189 / 192
页数:4
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