An Algorithm for the Search of a Low Capacitor Count DAC Switching Scheme for SAR ADCs

被引：1

作者：

Pilipko, Mikhail M. ^{[1
]}

Morozov, Dmitry V. ^{[1
]}

机构：

[1] Peter Great St Petersburg Polytech Univ, Inst Phys Nanotechnol & Telecommun, St Petersburg 195251, Russia

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2020年 / 39卷 / 12期

关键词：

Capacitors; Switches; Clocks; Digital-analog conversion; Analog-digital conversion; Energy resolution; Approximation algorithms; digital-analog conversion; dyadic rationals; iterative algorithms; tree graphs; CMOS;

D O I：

10.1109/TCAD.2020.2983132

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A search algorithm is presented for a switching scheme with a small number of unit capacitors for a digital-to-analog converter (DAC) used in a successive approximation register (SAR) analog-to-digital converter (ADC). The iterative algorithm is intended to build a binary tree for switching a charge-sharing DAC using a minimum possible number of capacitors. The resulting scheme does not increase the number of clock cycles for the binary search. The relationship between ADC resolution and the number of capacitors proves to be linear, in contrast to an exponential relationship usual for the capacitor arrays. Compared to a previously reported low-power and compact scheme, in a 10-bit case, a 76% reduction in capacitor count is achieved. The simulation results in a 65-nm CMOS technology with a sampling rate of 100 kS/s are presented.

引用

页码：5309 / 5313

页数：5

共 13 条

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