A Methodology for Automatic Insertion of Selective TMR in Digital Circuits Affected by SEUs

被引：44
作者：
Ruano, O. [1 ]
Maestro, J. A. [1 ]
Reviriego, P. [1 ]
机构：
[1] Univ Antonio Nebrija, E-28040 Madrid, Spain
来源：
IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2009年 / 56卷 / 04期
关键词：
Fault injection; optimization; single event upsets (SEUs); triple modular redundancy (TMR); SINGLE-EVENT UPSET; MITIGATION; SRAM;
D O I：
10.1109/TNS.2009.2014563
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, a methodology to perform automatic selective TMR insertion on digital circuits is presented, having as a constraint the required reliability level. Such reliability is guaranteed while reducing the area compared to TMR. In addition, a performance enhancement is proposed in order to guarantee a computation time feasible for this automatic selective TMR insertion methodology. It focuses on the choice of a starting point close enough to an optimal solution. The method consists in the analysis of the topological features of the target circuit which will help the optimization engine to identify those flip-flops more susceptible to be tripled depending on the showed sensitivity to SEUs.
引用
收藏
页码：2091 / 2102
页数：12
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