Investigation of Negative Capacitance Gate-all-Around Tunnel FETs Combining Numerical Simulation and Analytical Modeling

Ashort-channel negative capacitance gate-all-around tunnel field-effect transistor (NC-GAA-TFET) with a ferroelectric gate stack is proposed. Device performance is investigated by integrating three-dimensional (3-D) numerical simulation and the 1D Landau-Khalatnikov equation. It is shown that the NC-GAA-TFET has a steeper subthreshold swing and higher on-state current compared to conventional GAA-TFETs, and demonstrates no hysteretic behavior. Relevant analytical models, including the electrostatic potential model and the shortest tunnel path length (lsp), are developed to explain the device's operating principles and design optimization issues. Results from the analytical electrostatic potential model agree well with those of the numerical simulation. Furthermore, the analytical calculation shows that gate controllability over the channel is enhanced and the lsp value is significantly reduced as the thickness of the ferroelectric dielectric increases, resulting in better device characteristics. These results demonstrate the tremendous potential of NC-GAA-TFETs in low-power applications.