A digital calibration technique for timing mismatch in a four-channel time interleaved ADCs

被引:0
|
作者
Yin, Yong-Sheng [1 ]
Jian, Mao-Chen [1 ]
Chen, Hong-Mei [1 ]
机构
[1] Hefei Univ Technol, Inst VLSI Design, Hefei, Anhui, Peoples R China
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A digital calibration technique for timing mismatch in a four-channel time-interleaved ADCs is presented. The calibration principle is as follows. Firstly, we use delay units to have the clock of the first channel aligned with the channel that needs to be calibrated and do subtraction. Secondly, we use a digital sampling module and an error determination module to detect the timing mismatch between them. Lastly, a method of variable delay line is used to compensate the mismatch. The mismatch detection and compensation form a feedback loop that can achieve a real-time tracking and correcting. Simulation results showed that this technique can be applied to any channel TIADC and has the timing mismatch calibrated quickly and correctly by the virtue of a smaller hardware.
引用
收藏
页码:1546 / 1548
页数:3
相关论文
共 50 条
  • [1] A channel multiplexing digital calibration technique for timing mismatch of time-interleaved ADCs
    Yin, Yong-Sheng
    Liu, Liu
    Chen, Hong-Mei
    Deng, Hong-Hui
    Meng, Xu
    Wu, Jing-Sheng
    Wang, Zhong-Feng
    IEICE ELECTRONICS EXPRESS, 2019, 16 (19):
  • [2] A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs
    Li, Jing
    Wu, Shuangyi
    Liu, Yang
    Ning, Ning
    Yu, Qi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61 (07) : 486 - 490
  • [3] Blind calibration of timing offsets for four-channel time-interleaved ADCs
    Huang, Steven
    Levy, Bernard C.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (04) : 863 - 876
  • [4] An efficient digital calibration technique for timing mismatch in time-interleaved ADCs
    Chen Hongmei
    Jian Maochen
    Yin Yongsheng
    Lin Fujiang
    Cui Qing
    IEICE ELECTRONICS EXPRESS, 2016, 13 (13):
  • [5] Digital background calibration for timing mismatch in time-interleaved ADCs
    Chen, HH
    Lee, J
    Chen, JT
    ELECTRONICS LETTERS, 2006, 42 (02) : 74 - 75
  • [6] All-digital background calibration technique for timing mismatch of time-interleaved ADCs
    Chen, Hongmei
    Pan, Yunsheng
    Yin, Yongsheng
    Lin, Fujiang
    INTEGRATION-THE VLSI JOURNAL, 2017, 57 : 45 - 51
  • [7] A Novel Fully Digital Feedforward Background Calibration Technique for Timing Mismatch in M-Channel Time-Interleaved ADCs
    Xiong, Wei
    Zhang, Zhenwei
    Lang, Lili
    Dong, Yemin
    ELECTRONICS, 2023, 12 (09)
  • [8] A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors
    Law, Chi Ho
    Hurst, Paul J.
    Lewis, Stephen H.
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (10) : 2091 - 2103
  • [9] An Approximate Timing-Mismatch Calibration Technique for Interleaved ADCs
    Baran, Dursun
    Karav, Enes
    Yaren, Hakan
    2021 IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2021, : 644 - 647
  • [10] Correction of the Timing Mismatch Error in Four-Channel Time-Interleaved DACs
    Xu, Saihua
    Lee, Jun Wei
    2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2020,