A 10-Gb/s CMOS CDR and DEMUX IC with a quarter-rate linear phase detector

This paper presents a 10-Gb/s clock and data recovery (CDR) and demultiplexer IC in a 0.13-mu m CMOS process. The CDR uses a new quarter-rate linear phase detector, a new data recovery circuit, and a four-phase 2.5-GHz LC quadrature voltage-controlled oscillator for both wide phase error pulses and low power consumption. The chip consumes 100 mA from a 1.2-V core supply and 205 mA from a 2.5-V I/O supply including 18 preamplitiers and low voltage differential signal (LVDS) drivers. When 9.95328-Gb/s 2(31) - 1 pseudorandom binary sequence is used, the measured bit-error rate is better than 10-15 and the jitter tolerance is 0.5UI(pp), which exceeds the SONET OC-192 standard. The jitter of the recovered clock is 2.1 p(rms) at a 155.52 MHz monitoring clock pin. Multiple bit rates are supported from 9.4 Gb/s to 11.3 Gb/s.