Gate-Bias Induced Threshold Voltage ( $V_{TH}$ ) Instability in P-N Junction/AlGaN/GaN HEMT

In this work, we studied the threshold voltage ( $V_{TH}$ ) instability in E-mode p-n junction (PNJ)/AlGaN/GaN high-electron-mobility transistor (HEMT) using pulsed-I/V measurement and positive bias temperature instability (PBTI) test. $V_{TH}$ shifts positively under forward gate bias, which is ascribed to electron trapping in the gate-stack region. Benefiting from the special p-GaN/n-GaN junction, reduced electric field suppresses electron trapping in the PNJ gate, resulting in more stable $V_{TH}$ compared with the conventional Schottky-type p-GaN gate. Specifically, less positive threshold voltage shift ( $V_{TH}$ ) is observed under higher temperatures, or after being stressed for a prolonged period with gate bias exceeding 6 V. The decrease in positive $V_{TH}$ results from enhanced hole injection and especially hole trapping in the p-GaN/n-GaN interdiffusion region, which compensates for electron trapping and reduces positive $V_{TH}$ .