Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

被引：0

作者：

Raghavendra, R. G. ^{[1
]}

Amrutur, Bharadwaj ^{[1
]}

机构：

[1] Indian Inst Sci, Bangalore 560012, Karnataka, India

来源：

GLSVLSI'07: PROCEEDINGS OF THE 2007 ACM GREAT LAKES SYMPOSIUM ON VLSI | 2007年

关键词：

Dual-path loop filter;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 mu CSM analog process with 1.8V supply. The proposed circuits achieved up to 85% savings in capacitor area. Simulations showed good match of the new circuits with the conventional circuit. The proposed circuits are particularly useful in applications that demand low die area.

引用

页码：148 / 151

页数：4

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