Footer Voltage Controlled Dual Keeper Domino Logic with Static Switching Approach

In this paper, two circuits, namely Footer Voltage Controlled Dual Keeper domino logic (FVCDK) and Footer Voltage Controlled Dual Keeper with Static Switching domino logic (FVCDK-SS) are presented, in order to achieve high speed, low power consumption and robustness. The dual keeper arrangement helps in reducing the loop gain of the feedback circuitry, which leads to lower delay variability. The keeper circuitry is controlled using the footer voltage to reduce the contention current in the initial evaluation phase, and thus providing enhanced speed. In FVCDK-SS domino logic, unwanted transients at the output are reduced by incorporating pseudo-dynamic buffer in the proposed FVCDK domino logic. This further reduces the dynamic power consumption. The results of the logic presented here are validated by comparing them to a wide range of existing domino logic circuits for a variety of performance metrics such as delay, power, power-delay product and unity noise gain. To effectively gauge the wide fan-in capabilities of the proposed logic, results are shown for the various fan-in OR gate. The simulations of the circuits are carried out using industry standard full-suite Cadence tools using 45 nm technology library.