ARCHITECTURE AND IMPLEMENTATION OF REAL-TIME 3D STEREO VISION ON A XILINX FPGA

被引：0

作者：

Thomas, Sotiris ^{[1
]}

Papadimitriou, Kyprianos ^{[1
]}

Dollas, Apostolos ^{[1
]}

机构：

[1] Tech Univ Crete, Dept Elect & Comp Engn, GR-73100 Khania, Greece

来源：

2013 IFIP/IEEE 21ST INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION (VLSI-SOC) | 2013年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Many applications from autonomous vehicles to surveillance can benefit from real-time 3D stereo vision. In the present work we describe a 3D stereo vision design and its implementation that exploits effectively the resources of a Xilinx Virtex-5 FPGA. The post place-and-route design achieved a processing rate of 87 frames per sec (fps) for 1920 x 1200 resolution. The hardware prototype system was tested and validated for several data sets with resolutions up to 400 x 320 and we achieved a processing rate of 1570 fps.

引用

页码：186 / 191

页数：6

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