FPGA Implementation of An Efficient Montgomery Multiplier For Adaptive Filtering Application

Mini modern techniques rely on multiplication as the fundamental operation. Among the different ways of performing multiplication, Montgomery multiplication introduced by Peter Montgomery is the widely used algorithm. Despite improvements in the clock frequency and the level of parallelism of conventional microprocessors, software-based implementation of Montgomery multiplication remains insufficient in terms of both performance and energy efficiency. This has led to research investigating more efficient hardware accelerators. There are several techniques enhance the performance of Montgomery multiplier. The adaptive LMS filter is widely used in digital signal processing and communication. Adaptive filter has great application in noise cancellation. In this paper, we have the survey of various methods for hardware implementation of Montgomery multiplier and an efficient Montgomery multiplier is select for implementation in Adaptive LMS filter. The simulation results of realization adaptive LMS filters on a single FPGA chip is reported and the performances of Adaptive LMS filter with Montgomery multiplier is compare with normal Adaptive FIR filter. The LMS algorithm is less complex and suitable for hardware implementation. The digital adaptive LMS FIR filters were modeled by VHDL. The Xilinx software is used for synthesize and simulation of VHDL codes. Especially area and speed are the parameters taken into consideration. The time for Montgomery multiplication needs 4.75 mu s under the clock frequency of 113.09 MHz.