Design of FPGA's High-speed and Low-power Programmable Interconnect

This paper describes a fast interconnect scheme and the optimized circuit for FPGA programmable interconnects to achieve great performance and static power reduction. The fast interconnect scheme including fast connection between logic blocks and optimization of wire segments are proposed to reduce path delay and increase connectivity. Furthermore, non-minimum channel length technology is applied to routing circuits, which could effectively reduce static power dissipation. Experimental results show the optimized interconnect scheme can achieve 33.1% improvement of speed in average. With the optimization of non-minimum channel length technology, interconnect circuit can reduce up to 37.4% static power dissipation and even remain the speed.