Fast frequency acquisition phase-frequency detectors for GSamples/s phase-locked loops

被引：102

作者：

Mansuri, M

Liu, D ^{[1
]}

Yang, CKK

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

[2] Stanford Univ, Dept Elect Engn, Stanford, CA 94305 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2002年 / 37卷 / 10期

关键词：

clock generator; phase-frequency detector; phase-locked loop;

D O I：

10.1109/JSSC.2002.803048

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes two techniques for designing phase-frequency detectors (PFDs) with higher operating frequencies [periods of less than 8x the delay of a fan-out-4 inverter (FO-4)] and faster frequency acquisition. Prototypes designed in 0.25-mum CMOS process exhibit operating frequencies of 1.25 GHz [= 1/(8 (.) FO-4)] and 1.5 G14z [= 1/(6.7 - FO-4)] for two techniques, respectively, whereas a conventional PFD operates at <1 GHz 1/(10 (.) FO-4)]. The two proposed PFDs achieve a capture range of 1.7x and 1.4x the conventional design, respectively.

引用

页码：1331 / 1334

页数：4

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