A 12-b digital-background-calibrated algorithmic ADC with-90-dB THD

被引：73
作者：
Erdogan, OE [1 ]
Hurst, PJ [1 ]
Lewis, SH [1 ]
机构：
[1] Univ Calif Davis, Dept Elect & Comp Engn, Solid State Circuits Res Lab, Davis, CA 95616 USA
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1999年 / 34卷 / 12期
关键词：
adaptive systems; analog-digital conversion; calibration; CMOS analog integrated circuits;
D O I：
10.1109/4.808906
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate a 12-b algorithmic analog-to-digital converter in the background, At a sampling rate of 125 ksample/s and with monolithic background calibration, the peak signal-to-(noise + distortion) ratio is 71 dB, and the spurious-free dynamic range is 95 dB. The total power dissipation is 16 mW from 5 V. The active area is 5.9 mm(2) in 1.5-mu m CMOS.
引用
收藏
页码：1812 / 1820
页数：9
相关论文
共 19 条
[1]   An analog background calibration technique for time-interleaved analog-to-digital converters [J].
Dyer, KC ;
Fu, DH ;
Lewis, SH ;
Hurst, PJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :1912-1919
[2]   A digital background calibration technique for time-interleaved analog-to-digital converters [J].
Fu, DH ;
Dyer, KC ;
Lewis, SH ;
Hurst, PJ .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :1904-1911
[3]   A continuously calibrated 12-b, 10-MS/s, 3.3-V A/D converter [J].
Ingino, JM ;
Wooley, BA .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) :1920-1931
[4]   A 12b 128MSample/s ADC with 0.05LSB DNL [J].
Jewett, R ;
Poulton, K ;
Hsieh, KC ;
Doernberg, J .
1997 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE - DIGEST OF TECHNICAL PAPERS, 1997, 40 :138-139
[5]   A 15-B 1-MSAMPLE/S DIGITALLY SELF-CALIBRATED PIPELINE ADC [J].
KARANICOLAS, AN ;
LEE, HS ;
BACRANIA, KL .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1993, 28 (12) :1207-1215
[6]   A 15-b, 5-Msample/s low-spurious CMOS ADC [J].
Kwak, SU ;
Song, BS ;
Bacrania, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (12) :1866-1875
[7]   A 12-B 600-KS/S DIGITALLY SELF-CALIBRATED PIPELINED ALGORITHMIC ADC [J].
LEE, HS .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1994, 29 (04) :509-515
[8]   A SELF-CALIBRATING 15 BIT CMOS A/D CONVERTER [J].
LEE, HS ;
HODGES, DA ;
GRAY, PR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (06) :813-819
[9]   A PIPELINED 5-MSAMPLE/S 9-BIT ANALOG-TO-DIGITAL CONVERTER [J].
LEWIS, SH ;
GRAY, PR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1987, 22 (06) :954-961
[10]   A RATIO-INDEPENDENT ALGORITHMIC ANALOG-TO-DIGITAL CONVERSION TECHNIQUE [J].
LI, PW ;
CHIN, MJ ;
GRAY, PR ;
CASTELLO, R .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (06) :828-836
12