共 11 条
[1]
[Anonymous], 2011, P 2011 INT C HIGH PE
[2]
The PARSEC Benchmark Suite: Characterization and Architectural Implications
[J].
PACT'08: PROCEEDINGS OF THE SEVENTEENTH INTERNATIONAL CONFERENCE ON PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES,
2008,
:72-81
[3]
Binkert Nathan, 2011, Computer Architecture News, V39, P1, DOI 10.1145/2024716.2024718
[4]
Feitelson D. G., 1998, Job Scheduling Strategies for Parallel Processing. IPPS/SPDP'98 Workshop Proceedings, P1, DOI 10.1007/BFb0053978
[5]
Florea A, 2014, INT CONF SYST THEO, P31, DOI 10.1109/ICSTCC.2014.6982386
[6]
Genbrugge D., 2010, HIGH PERFORMANCE COM, P1
[7]
Heirman W, 2011, I S WORKL CHAR PROC, P38, DOI 10.1109/IISWC.2011.6114195
[8]
Henkel J, 2012, ASIA S PACIF DES AUT, P193, DOI 10.1109/ASPDAC.2012.6164944
[9]
Performance-Aware Resource Management of Multi-Threaded Applications on Many-Core Systems
[J].
PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2017 (GLSVLSI' 17),
2017,
:119-124
[10]
Sheng Li, 2009, Proceedings of the 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2009), P469