On-Chip Measurement of Jitter Transfer and Supply Sensitivity of PLL/DLLs

This brief describes low-cost on-chip measurement circuits for jitter transfer and supply sensitivity of phase-locked loops (PLLs) and delay-locked loops (DLLs). Unlike previous works that measured the frequency-domain responses, the proposed circuits measure the time-domain responses of the PLL/DLL to the periodic disturbances applied to either it,; input clock phase or its supply voltage. A synchronous sampling technique accurately measures the PLL/DLL's periodic response. while suppressing the unrelated noises and interferences via averaging. The synchronous sampler outputs either dc voltage or digital values, making it suitable for low-cost characterization and production tests. The procedure for estimating the frequency-domain transfer functions from the measured time-domain responses is outlined. The jitter transfer and supply sensitivity measurements were demonstrated with a PLL fabricated in 0.13-mu m CMOS. Compared with the PLL that occupied 1.1 x 0.46 mm(2) and dissipated 36 mW from a 1.2-V supply, the on-chip measurement circuits occupied only 0.01.4 mm(2) and dissipated only 2.6 mW.