Highly Enhanced Performance of Network Channel Polysilicon Thin-Film Transistors

被引：5

作者：

Lee, Hojoon ^{[1
]}

Lee, Junyoung ^{[1
]}

Baek, Sangwon ^{[1
]}

Jeong, Woong Hee ^{[2
]}

Lee, Yongsu ^{[2
]}

Yang, Taehoon ^{[2
]}

Lee, Jeong-Soo ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol, Dept Elect Engn, Pohang 37673, South Korea

[2] Samsung Display Co Ltd, Asan 31454, South Korea

来源：

IEEE ELECTRON DEVICE LETTERS | 2017年 / 38卷 / 02期

基金：

新加坡国家研究基金会;

关键词：

Grain boundary; thin film transistor; LTPS; low-frequency noise; hot carrier injection; SILICON; MOSFETS; DENSITY; MEMORY; TFT;

D O I：

10.1109/LED.2016.2636924

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter presents the electrical characteristics of newly proposed network-channel low-temperature polysilicon channel (LTPS) thin-film transistors (TFTs). Due to effective reduction of grain boundary traps and enhanced gate controllability, the network-channel TFTs show better subthreshold slope, lower threshold voltage, and higher ON-OFF current ratio, compared with conventional planar devices. The extracted grain boundary trap density and the interface trap density are significantly reduced in the network-channel devices. In addition, the network-channel devices show higher immunity to hot-carrier stressing, which are confirmed from the low-frequency noise characteristics with various stressing time. These results suggest that the network-channel devices are very promising for next-generation LTPS TFT applications.

引用

页码：187 / 190

页数：4

共 16 条

[1]

Chang KM, 2001, IEEE ELECTR DEVICE L, V22, P475, DOI 10.1109/55.954916

[2] Negative bias temperature instability in low-temperature polycrystalline silicon thin-film transistors [J].

Chen, Chih-Yang ;

Lee, Jain-Wem ;

Wang, Shen-De ;

Shieh, Ming-Shan ;

Lee, Po-Hao ;

Chen, Wei-g Chen ;

Lin, Hsiao-Yi ;

Yeh, Kuan-Lin ;

Lei, Tan-Fu .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (12) :2993-3000

[3] A novel nanowire channel poly-Si TFT functioning as transistor and nonvolatile SONOS memory [J].

Chen, Shih-Ching ;

Chang, Ting-Chang ;

Liu, Po-Tsun ;

Wu, Yung-Chun ;

Lin, Po-Shun ;

Tseng, Bae-Heng ;

Shy, Jang-Hung ;

Sze, S. M. ;

Chang, Chun-Yen ;

Lien, Chen-Hsin .

IEEE ELECTRON DEVICE LETTERS, 2007, 28 (09) :809-811

[4] SUBTHRESHOLD SLOPE OF THIN-FILM SOI MOSFETS [J].

COLINGE, JP .

IEEE ELECTRON DEVICE LETTERS, 1986, 7 (04) :244-246

[5] High performance fully-depleted tri-gate CMOS transistors [J].

Doyle, BS ;

Datta, S ;

Doczy, M ;

Hareland, S ;

Jin, B ;

Kavalieros, J ;

Linton, T ;

Murthy, A ;

Rios, R ;

Chau, R .

IEEE ELECTRON DEVICE LETTERS, 2003, 24 (04) :263-265

[6] Optimal integration and characteristics of vertical array devices for ultra-high density, Bit-Cost Scalable flash memory [J].

Fukuzumi, Yoshiaki ;

Katsumata, Ryota ;

Kito, Masaru ;

Kido, Masaru ;

Sato, Mitsuru ;

Tanaka, Hiroyasu ;

Nagata, Yuzo ;

Matsuoka, Yasuyuki ;

Iwata, Yoshihisa ;

Aochi, Hideaki ;

Nitayama, Akihiro .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :449-+

[7] Evaluation of grain boundary trap states in polycrystalline-silicon thin-film transistors by mobility and capacitance measurements [J].

Ikeda, H .

JOURNAL OF APPLIED PHYSICS, 2002, 91 (07) :4637-4645

[8] A 1/F NOISE TECHNIQUE TO EXTRACT THE OXIDE TRAP DENSITY NEAR THE CONDUCTION-BAND EDGE OF SILICON [J].

JAYARAMAN, R ;

SODINI, CG .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (09) :1773-1782

[9] CONDUCTIVITY BEHAVIOR IN POLYCRYSTALLINE SEMICONDUCTOR THIN-FILM TRANSISTORS [J].

LEVINSON, J ;

SHEPHERD, FR ;

SCANLON, PJ ;

WESTWOOD, WD ;

ESTE, G ;

RIDER, M .

JOURNAL OF APPLIED PHYSICS, 1982, 53 (02) :1193-1202

[10] A proposed single grain-boundary thin-film transistor [J].

Oh, CH ;

Matsumura, M .

IEEE ELECTRON DEVICE LETTERS, 2001, 22 (01) :20-22

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