Real-Time FPGA Simulation of Electric Ship Power System Using High-Level Synthesis

In this paper, we present an approach to model simulation systems at the Register-Transistor Level RTL for an efficient implementation on Field Programmable Gate Arrays FPGAs. The process uses a hybrid technique utilizing two commercially available tools, Simulink Coder and Xilinx Vivado HLD, as well as a middleware procedure to produce an accurate implementation of a model system in HDL, e.g. Verilog and VHDL. The implementation technique does not require expertise knowledge in Digital Design or Hardware Description Language HDL, yet it produces a complete description of the simulator in HDL. Using an example model of electric ship power system, we evaluate the effectiveness of the approach in developing a precise model in RTL for Real-Time simulation while accelerating the overall execution time.