An iterative calculation method of the neuron model for hardware implementation

被引：0

作者：

Chujo, N ^{[1
]}

Kuroyanagi, S ^{[1
]}

Doki, S ^{[1
]}

Okuma, S ^{[1
]}

机构：

[1] Toyota Cent R&D Labs Inc, Nagakute, Aichi 4801192, Japan

来源：

IECON 2000: 26TH ANNUAL CONFERENCE OF THE IEEE INDUSTRIAL ELECTRONICS SOCIETY, VOLS 1-4: 21ST CENTURY TECHNOLOGIES AND INDUSTRIAL OPPORTUNITIES | 2000年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Artificial Neural Networks (ANN) have potential of the parallel processing by the integrated circuit technology. Recently, over one million gates are available by the latest FPGA (Field Programmable Gate Array). However, the sum-of-product circuit used for evaluating inputs of the neuron model is complex and not effective for hardware implementation by FPGAs. In this paper, an improved calculation algorithm of the perceptron-type neuron, model is proposed. which is based on the multi-dimensional binary search. Since the search doesn't need the sum-of-product circuit. the designed neuron circuit is small and fast. It is suitable for hardware implementation,.

引用

页码：664 / 671

页数：8

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