Worst Case Test Vectors for Sequential Circuits in Flash-Based FPGAs Exposed to Total Dose

被引：1

作者：

Abdelwahab, M. S. ^{[1
,3
]}

Abdel-Aziz, M. M. ^{[2
]}

Abdelgawad, M. M. ^{[3
]}

Abou-Auf, A. A. ^{[3
]}

Ibrahim, M. A. ^{[3
]}

机构：

[1] Si Vision LLC, Cairo 11361, Egypt

[2] Cairo Univ, Dept Comp Engn, Cairo 12613, Egypt

[3] Amer Univ Cairo, Dept Elect & Commun Engn, New Cairo 11835, Egypt

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 2019年 / 66卷 / 07期

关键词：

Design for testability (DFT); field-programmable gate arrays (FPGAs); path delay faults; testing techniques; total-dose testing; DESIGN;

D O I：

10.1109/TNS.2019.2920449

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We introduce a methodology for identifying worst case test vectors (WCTVs) for delay failures induced by total dose in sequential circuits implemented in flash-based field-programmable gate arrays (FPGAs) using design-for-testability (DFT) techniques and path delay faults using commercially available DFT and automatic test pattern generation (ATPG) tools. We verified this methodology experimentally using Microsemi ProASiC3 FPGAs and Cobalt 60 facility. The experimental results show a significant impact on the total dose failure level when using WCTVs in total-dose testing of FPGA devices.

引用

页码：1642 / 1650

页数：9

共 14 条

[1] Fault Modeling and Worst Case Test Vector Generation for Flash-Based FPGAs Exposed to Total Dose [J].

Abou-Auf, A. A. ;

Abdel-Aziz, M. M. ;

Abdel-Aziz, M. A. ;

Ammar, A. A. .

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, 2017, 64 (08) :2250-2258

[2]

BRGLEZ F, 1989, 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, P1929, DOI 10.1109/ISCAS.1989.100747

[3]

Bushnell M. L., 2000, ESSENTIALS ELECT TES, P417

[4] Classification and identification of nonrobust untestable path delay faults [J].

Cheng, KT ;

Chen, HC .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1996, 15 (08) :845-853

[5] DELAY-FAULT TEST-GENERATION AND SYNTHESIS FOR TESTABILITY UNDER A STANDARD SCAN DESIGN METHODOLOGY [J].

CHENG, KT ;

DEVADAS, S ;

KEUTZER, K .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1993, 12 (08) :1217-1231

[6] Survey of low-power testing of VLSI circuits [J].

Girard, P .

IEEE DESIGN & TEST OF COMPUTERS, 2002, 19 (03) :82-92

[7] Unveiling the ISCAS-85 benchmarks: A case study in reverse engineering [J].

Hansen, MC ;

Yalcin, H ;

Hayes, JP .

IEEE DESIGN & TEST OF COMPUTERS, 1999, 16 (03) :72-80

[8] BIST-based delay path testing in FPGA architectures [J].

Harris, IG ;

Menon, PR ;

Tessier, R .

INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, :932-938

[9]

Krstic A., 1998, DELAY FAULT TESTING, P27

[10] Robust system design with built-in soft-error resilience [J].

Mitra, S ;

Seifert, N ;

Zhang, M ;

Shi, Q ;

Kim, KS .

COMPUTER, 2005, 38 (02) :43-+

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