Low Power Full Adder Using 8T Structure

被引：0
作者：
Bazzazi, Amin [1 ]
Mahini, Alireza [1 ]
Jelini, Jelveh [1 ]
机构：
[1] Islamic Azad Univ, Dept Comp Engn, Gorgan Branch, Gorgan, Iran
来源：
INTERNATIONAL MULTICONFERENCE OF ENGINEERS AND COMPUTER SCIENTIST, IMECS 2012, VOL II | 2012年
关键词：
Full Adder; Low Power; CMOS; Delay;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A low power and high performance 1-bit full adder cell is proposed. The 8T Full Adder technique has been used for the generation of XOR function. Twelve state-of-theart 1-bit full adders and one proposed full adder are simulated with HSPICE using 0.18 mu m CMOS Technology at 1.8V supply voltage. By optimizing the transistor size in each stage the power and delay are minimized. The results of post-layout. simulation compared to similar reported ones illustrate significant improvement. Simulation results show great improvement in terms of Power-Delay-Product (PDP). The power consumption of this adder is 200nw.
引用
收藏
页码：1190 / 1194
页数：5
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