An Ultra Low-Power 24 GHz Phase-Lock-Loop with Low Phase-Noise VCO Embedded in 0.18 μm CMOS Process

A 24 GHz 29.8 mW Phase-lock-loop using 0.18 mu m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm(2) without off-chip loop filter.