An Ultra Low-Power 24 GHz Phase-Lock-Loop with Low Phase-Noise VCO Embedded in 0.18 μm CMOS Process

被引：0

作者：

Yu-Hsuan, Lin ^{[1
,2
]}

Tsai, Jeng-Han ^{[3
]}

Kuo, Yen-Hung ^{[1
,2
]}

Huang, Tian-Wei ^{[1
,2
]}

机构：

[1] Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan

[2] Natl Taiwan Univ, Grad Inst Commun Engn, Taipei 106, Taiwan

[3] Natl Taiwan Normal Univ, Dept Appl Elect Technol, Taipei 106, Taiwan

来源：

ASIA-PACIFIC MICROWAVE CONFERENCE 2011 | 2011年

关键词：

CMOS; Phase-Lock-Loop (PLL); VCO; Injection-Locked Frequency Divider(ILFD);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 24 GHz 29.8 mW Phase-lock-loop using 0.18 mu m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by -122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm(2) without off-chip loop filter.

引用

页码：1630 / 1633

页数：4

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