Low-power direct digital frequency synthesis for wireless communications

被引：112

作者：

Bellaouar, A ^{[1
]}

O'brecht, MS ^{[1
]}

Fahim, AM ^{[1
]}

Elmasry, MI ^{[1
]}

机构：

[1] Univ Waterloo, Dept Elect & Comp Engn, VLSI Res Grp, Waterloo, ON N2L 3G1, Canada

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2000年 / 35卷 / 03期

基金：

加拿大自然科学与工程研究理事会;

关键词：

digital circuits; direct digital synthesis (DDS); low-power; wireless communications;

D O I：

10.1109/4.826821

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A low-power direct digital frequency synthesizer (DDFS) architecture is presented. It uses a smaller lookup table for sine and cosine functions compared to already existing systems with a minimum additional hardware. Only 16 points are stored in the internal memory implemented in ROM (read-only memory). The full computation of the generated sine and cosine is based on the linear interpolation between the sample points. A DDFS with 60-dBc spectral purity, 29-Hz frequency resolution, and 9-bit output data for sine function generation is being implemented in 0.8-mu m CMOS technology. Experimental results verify that the average power dissipation of the DDFS logic is 9.5 mW (at 30 MHz, 3.3 V).

引用

页码：385 / 390

页数：6

共 13 条

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Bellaouar, A
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Fahim, A
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