Efficient On-Chip Crosstalk Avoidance CODEC Design

被引：72

作者：

Duan, Chunjie ^{[1
]}

Calle, Victor H. Cordero ^{[2
]}

Khatri, Sunil P. ^{[2
]}

机构：

[1] Mitsubishi Elect Res Labs, Cambridge, MA 02139 USA

[2] Texas A&M Univ, Dept Elect & Comp Engn, College Stn, TX 77843 USA

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2009年 / 17卷 / 04期

关键词：

CODEC; crosstalk; Fibonacci number; on-chip bus;

D O I：

10.1109/TVLSI.2008.2005313

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Interconnect delay has become a limiting factor for circuit performance in deep sub-micrometer designs. As the crosstalk in an on-chip bus is highly dependent on the data patterns transmitted on the bus, different crosstalk avoidance coding schemes have been proposed to boost the bus speed and/or reduce the overall energy consumption. Despite the availability of the codes, no systematic mapping of datawords to codewords has been proposed for CODEC design. This is mainly due to the nonlinear nature of the crosstalk avoidance codes (CAC). The lack of practical CODEC construction schemes has hampered the use of such codes in practical designs. This work presents guidelines for the CODEC design of the "forbidden pattern free crosstalk avoidance code" (FPF-CAC). We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists based on the representation of numbers In the Fibonacci numeral system. Our first proposed CODEC design offers a near-optimal area overhead performance. An Improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed.

引用

页码：551 / 560

页数：10

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