Modeling substrate noise generation in CMOS digital integrated circuits

被引：12

作者：

Nagata, M ^{[1
]}

Morie, T ^{[1
]}

Iwata, A ^{[1
]}

机构：

[1] Hiroshima Univ, Integrated Syst Lab, Higashihiroshima 7398526, Japan

来源：

PROCEEDINGS OF THE IEEE 2002 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2002年

关键词：

D O I：

10.1109/CICC.2002.1012889

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A time-series divided parasitic capacitance model accurately simulates substrate noise generation of practical CMOS digital integrated circuits in time domain. The simulation of a 0.25-mum z80 micro-controller with 62.5-MHz clock frequency costs less than 10 sec. per a clock cycle including the model generation. Simulated substrate noise well consists with 200-ps 100-muV resolution measurements in wave-shapes validated for clock frequency up to 125 MHz and shows the peak-amplitude error of less than 2% against supply-voltage scaling from 2.5 V to 1.6 V.

引用

页码：501 / 504

页数：4

共 8 条

[1] Modeling digital substrate noise injection in mixed-signal IC's [J].