Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time

被引：11

作者：

Jeong, Hanwool ^{[1
,2
]}

Park, Juhyun ^{[1
]}

Song, Seung Chul ^{[3
]}

Jung, Seong-Ook ^{[1
]}

机构：

[1] Yonsei Univ, Sch Elect & Elect Engn, Seoul 03722, South Korea

[2] Samsung Elect Co Ltd, Yongin 17113, South Korea

[3] Qualcomm Inc, San Diego, CA 92121 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2019年 / 54卷 / 08期

关键词：

Flip-flop; low power; low voltage; pulsed latch; variation-aware; TRIGGERED FLIP-FLOP; DESIGN;

D O I：

10.1109/JSSC.2019.2907774

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A self-timed pulsed latch (STPL) is proposed for low VDD operation. By comparing input and output, the transparency window is adaptively generated in STPL, which resolves the hold time problem of the conventional pulsed latch. The measurement results from the test chip fabricated in the 65-nm technology proves that the hold time is reduced by 77% and the minimum operating supply voltage is lowered by 300 mV compared with the conventional pulsed latch. In addition, the measurement results show that the STPL can reduce the sequential overhead, because the STPL is free from setup time issue from which the conventional master-slave-based flip-flop (MSFF) suffers. The simulation results show that the input-to-output delay of STPL, which also determines the sequential overhead, is smaller by 45% in 0.6 V compared with that of the MSFF structure.

引用

页码：2304 / 2315

页数：12