Low-power logic circuit and SRAM cell applications with silicon on depletion layer CMOs (SODEL CMOS) technology

In this paper, the switching performance of Silicon on Depletion Layer CMOS (SODEL CMOS) [1] is investigated with a view to realizing high-speed and low-power CMOS applications. Thanks to smaller parasitic capacitance, the propagation delay time (tau(pd)) in SODEL CMOS has been improved by up to 25% compared to that of conventional bulk CMOS in five stacked nFET inverters at the same Vdd. It is also confirmed that about 30% better power-delay product can be realized at the same -rpd with reduced Vdd in SODEL CMOS. In SRAM cell applications, SODEL CMOS shows high Static Noise Margin (SNM) of similar to 95 mV at V-dd = 0.6 V. Smaller bit-line delay is expected and confirmed in SODEL CMOS SRAM by SPICE simulations. Latch-up immunity for a-particle irradiation in SODEL CMOS was also found to be comparable to that of conventional bulk CMOS. Therefore, SODEL CMOS device and circuit technology is expected to provide a better solution for low-power system-on-a-chip (SoC).