A Novel High Speed MCML Square Root Carry Select Adder for Mixed-Signal Applications

被引：0

作者：

Gupta, Kirti ^{[1
]}

Radhika ^{[1
]}

Pandey, Neeta ^{[1
]}

Gupta, Maneesha ^{[2
]}

机构：

[1] Delhi Technol Univ, Elect & Commun Dept, New Delhi, India

[2] Univ Delhi, NSIT, Dept Elect & Commun, Delhi 110007, India

来源：

2013 INTERNATIONAL CONFERENCE ON MULTIMEDIA, SIGNAL PROCESSING AND COMMUNICATION TECHNOLOGIES (IMPACT) | 2013年

关键词：

MCML; RCA; Square Root Carry Select Adder; High Speed;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS and MCML styles and 16bit CMOS SQ-CSA. It is found that the proposed 16-bit MCML SQ-C SA reduces the worst case delay by 67.50% and 72.49% in comparison to the MCML and CMOS based RCAs respectively. Also, the proposed 16-bit MCML SQ-CSA adder results in 26.55% reduction in delay in comparison to CMOS SQ-CSA. In terms of power consumption, the proposed MCML SQ-CSA shows a reduction of 58.97% in comparison to CMOS SQ-CSA.

引用

页码：194 / 197

页数：4

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