A Novel High Speed MCML Square Root Carry Select Adder for Mixed-Signal Applications

被引：0
|
作者：
Gupta, Kirti [1 ]
Radhika [1 ]
Pandey, Neeta [1 ]
Gupta, Maneesha [2 ]
机构：
[1] Delhi Technol Univ, Elect & Commun Dept, New Delhi, India
[2] Univ Delhi, NSIT, Dept Elect & Commun, Delhi 110007, India
来源：
2013 INTERNATIONAL CONFERENCE ON MULTIMEDIA, SIGNAL PROCESSING AND COMMUNICATION TECHNOLOGIES (IMPACT) | 2013年
关键词：
MCML; RCA; Square Root Carry Select Adder; High Speed;
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a MOS current mode logic (MCML) square root carry select adder (SQ-CSA) which can be used as an alternative to MCML ripple carry adder (RCA) when the number of bits in the input words is large. The proposed 16-bit MCML SQ-CSA has been implemented and simulated in PSPICE using TSMC 180 nm CMOS technology parameters. Its performance has been compared with 16-bit RCAs based on CMOS and MCML styles and 16bit CMOS SQ-CSA. It is found that the proposed 16-bit MCML SQ-C SA reduces the worst case delay by 67.50% and 72.49% in comparison to the MCML and CMOS based RCAs respectively. Also, the proposed 16-bit MCML SQ-CSA adder results in 26.55% reduction in delay in comparison to CMOS SQ-CSA. In terms of power consumption, the proposed MCML SQ-CSA shows a reduction of 58.97% in comparison to CMOS SQ-CSA.
引用
收藏
页码：194 / 197
页数：4
相关论文
共 50 条
  • [1] An energy and area efficient yet high-speed square-root carry select adder structure
    Bahadori, Milad
    Kamal, Mehdi
    Afzali-Kusha, Ali
    Pedram, Massoud
    COMPUTERS & ELECTRICAL ENGINEERING, 2017, 58 : 101 - 112
  • [2] Comparative Analysis of Different Architectures of MCML Square Root Carry Select Adders for Low-Power Applications
    Jain, Ginni
    Vyas, Keerti
    Maurya, Vijendra K.
    Patel, Mayank
    PROCEEDINGS OF INTERNATIONAL CONFERENCE ON ICT FOR SUSTAINABLE DEVELOPMENT ICT4SD 2015, VOL 2, 2016, 409 : 299 - 306
  • [3] ASIC Implementation of High-Speed Adaptive Recursive Karatsuba Multiplier with Square-Root-Carry-Select-Adder
    Naik, Akhilesh
    Deka, Debarshi
    Pal, Dipankar
    2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), 2020,
  • [4] Design of high speed hybrid carry select adder
    Parmar, Shivani
    Singh, Kirat Pal
    PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC), 2013, : 1656 - 1663
  • [5] A Novel Implementation of High Speed Modified Brent Kung Carry Select Adder
    Hepzibha, K. Golda
    Subha, C. P.
    PROCEEDINGS OF THE 10TH INTERNATIONAL CONFERENCE ON INTELLIGENT SYSTEMS AND CONTROL (ISCO'16), 2016,
  • [6] High Speed Square Root Carry Select Adder Using MTCMOS D-Latch in 45nm Technology
    Das, Adyasha
    Mandal, Sushanta K.
    Das, Jitendra K.
    2015 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, SIGNALS, COMMUNICATION AND OPTIMIZATION (EESCO), 2015,
  • [7] Design of Low Power and High-Speed 16-bit Square Root Carry Select Adder using AL
    Bajpai, Archit
    Anuraj, A. R.
    Shakthivel, G.
    Premananda, B. S.
    2018 3RD INTERNATIONAL CONFERENCE ON CIRCUITS, CONTROL, COMMUNICATION AND COMPUTING (I4C), 2018,
  • [8] Design of area efficient and Low power Square Root Carry Select Adder
    Jayachandran, T.
    Sharmilee, K.
    Sangeetha, K. K.
    BIOSCIENCE BIOTECHNOLOGY RESEARCH COMMUNICATIONS, 2020, 13 (06): : 153 - 156
  • [9] Enhanced Low-Power Digital Signal Processing via a Novel Reversible MCML-Based Carry Select Adder
    Shanmugam, Sharmila Devi
    TRAITEMENT DU SIGNAL, 2024, 41 (02) : 1043 - 1048
  • [10] Design of Carry Select Adder for Low-Power and High Speed VLSI Applications
    Naik, M. Vinod Kumar
    Aneesh, Mohammed Y.
    2015 IEEE INTERNATIONAL CONFERENCE ON ELECTRICAL, COMPUTER AND COMMUNICATION TECHNOLOGIES, 2015,
12345