Analysis of Metastability in Pipelined ADCs

被引：23

作者：

Hashemi, Sedigheh ^{[1
]}

Razavi, Behzad ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2014年 / 49卷 / 05期

关键词：

Average conductance; metastability; multi-bit stage; multiplying DAC; pipelined ADCs; sub-ADC;

D O I：

10.1109/JSSC.2014.2305075

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A critical issue in the design of high-speed ADCs relates to the errors that result from comparator metastability. Studied for flash architectures in the past, this phenomenon assumes new dimensions in pipelined converters, creating far more complex error mechanisms. This paper presents a comprehensive analysis of comparator metastability effects in pipelined ADCs and develops a method to predict the error behavior for a given input signal PDF Different error mechanisms are identified and formulated to obtain the probability of error versus the magnitude of error. An 8-bit 600 MS/s ADC fabricated in 65 nm CMOS technology has been used to assess the validity of the analytical results.

引用

页码：1198 / 1209

页数：12

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