LOW-COMPLEXITY HIGH-SPEED 4-D TCM DECODER

被引：0

作者：

He, Jinjin ^{[1
]}

Wang, Zhongfeng ^{[1
]}

Liu, Huaping ^{[1
]}

机构：

[1] Oregon State Univ, Sch EECS, Corvallis, OR 97331 USA

来源：

2008 IEEE WORKSHOP ON SIGNAL PROCESSING SYSTEMS: SIPS 2008, PROCEEDINGS | 2008年

关键词：

VLSI; FPGA; Trellis coded modulation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture for the transition metrics unit (TMU) is proposed to significantly reduce the computation complexity without degrading the performance. In addition, pipelining and parallel processing techniques are exploited to increase the decoding throughput. Synthesis results show that the FPGA implementation of the TCM decoder can achieve a maximum throughput of 1.062 Gbps.

引用

页码：216 / 220

页数：5

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