A 1.8-V 22-mW 10-bit 30-MS/s subsampling pipelined CMOS ADC

This paper describes a 10-bit 30-MS/s subsampling pipelined ADC that is implemented in a 0.18 mu m CMOS process. The ADC adopts a power efficient amplifier sharing architecture in which a set of switches is introduced to reduce the influence between the two opamp-sharing successive stages. A new configuration is used in the first stage of the ADC to avoid using a dedicated sample-and-hold amplifier (SHA) circuit at the input and to avoid the matching requirement between the first multiplying digital-to-analog converter (MDAC) and flash input signal paths, which is very strict in a traditional SHA-less architecture. The measured differential and integral nonlinearities of the prototype show less than 0.57 least significant bit (LSB) and 0.8 LSB respectively at full sampling rate. The ADC exhibits higher than 9.1 effective number of bits (ENOB) for input frequencies up to 30 MHz, which is the twofold Nyquist rate (fs/2), at 30 MS/s. The ADC consumes 21.6 mW from a 1.8-V supply and occupies 0.7 mm(2), which also includes the bandgap and buffer amplifiers.