A novel fault tolerant cache to improve yield in nanometer technologies

Process parameter variations are expected to be significantly high in sub-50 nm technology regime, which can severely affect the yield, unless very conservative design techniques are employed. The parameter variations are random in nature and are expected to be more pronounced in minimum geometry transistors commonly used in memories such as SRAM. Consequently, a large number of cells in a memory are expected to be faulty due to variations in different process parameters. In this paper we analyze SPUM cellfailure under process variation andpropose a newfault tolerant cache architecture suitable for high performance applications. The faulty cells are dynamically detected and replaced by adaptively resizing the cache. The granularity of our resizing technique is low and hence, the technique can handle a large number of faults. This scheme is transparent to processor architecture and has negligible energy and area overhead. This scheme also does not affect the cache access time and has minimum effect on processor performance. Experimental results on a 64K cache implemented using BPTM (Berkeley Predictive Technology Model) 45 nm technology show that using our technique the effective yield can be increased to 94%from its original 33%.