A 15-20GHz Delay-Locked Loop in 90nm CMOS Technology

被引：2
|
作者：
Chang, Jung-Yu [1 ]
Chuang, Chi-Nan [1 ]
Liu, Shen-Iuan [1 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10617, Taiwan
来源：
2008 IEEE ASIAN SOLID-STATE CIRCUITS CONFERENCE | 2008年
关键词：
D O I：
10.1109/ASSCC.2008.4708766
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 15GHz-20GHz delay-locked loop (DLL) has been fabricated in 90nm CMOS technology. It not only relaxes the speed requirement of the voltage-controlled delay line (VCDL), but also allows the VCDL not to operate at the highest frequency. When this DLL operates at 20GHz, the measured root-mean-square and peak-to-peak jitters are 0.813ps and 6.62ps, respectively. The core area is 0.250.4 mm(2) and the power consumption is 49mW for 0.9V supply.
引用
收藏
页码：213 / 216
页数：4
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