CMOS ring oscillator with combined delay stages

被引：56

作者：

Ramazani, Abbas ^{[1
]}

Biabani, Sadegh ^{[2
]}

Hadidi, Gholamrea ^{[3
]}

机构：

[1] Lorestan Univ, Dept Elect Engn, Khorramabad, Iran

[2] Shahid Beheshti Univ, Microelect Lab, Tehran, Iran

[3] Hamedan Univ Technol, Dept Elect Engn, Hamadan, Iran

来源：

AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS | 2014年 / 68卷 / 06期

关键词：

CMOS; Ring oscillator; Inverter; Frequency stability;

D O I：

10.1016/j.aeue.2013.12.008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Full transistor voltage control oscillators by delay stages are studied in this paper. First we describe the general conditions of oscillators and after introducing some common inverters, calculating their delay times, we analyze the dependence of delay time to variation of power supply voltage. The analyzing results show that the delay of basic type inverter varies in the opposite direction as that of current starved inverter, therefore to achieve better frequency stability versus voltage power supply changing, some combined structures of inverters are presented. The results of simulation by 0.18 CMOS technology library of HSPICE approve the analysis results. (C) 2013 Elsevier GmbH. All rights reserved.

引用

页码：515 / 519

页数：5

共 6 条

[1]

Jovanovic G., 2010, Scientific Publications of the State University of Novi Pazar, Series A: Applied Mathematics, Informatics and mechanics, V2, P1

[2] A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching [J].