An AVS Video Decoder Design and Implementation Based On Parallel Algorithm

被引：0
|
作者：
Sui, Chunchun [1 ]
Wang, Ning [2 ]
Chen, Ling [1 ]
Cao, Xixin [1 ]
机构：
[1] Peking Univ, Sch Softwar & Microelect, Beijing, Peoples R China
[2] Xidian Univ, Inst Microelect, Xian, Peoples R China
来源：
12TH INTERNATIONAL CONFERENCE ON ADVANCED COMMUNICATION TECHNOLOGY: ICT FOR GREEN GROWTH AND SUSTAINABLE DEVELOPMENT, VOLS 1 AND 2 | 2010年
关键词：
Videodecoder; Parallelism processing; CC1100; AVS;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
With the development of communication, digital video compression technology turns into one of the most flourishing realm. In this paper the author introduces an AVS decoder design based on a multimedia chip-platform. In order to obtain the optimal performance, the structure of decoder adopts parallel algorithm with the centre processer and the coprocessor. The performance of the decoder which is about ten times faster than that of the software mode rm52j_r1, meets the requirement of real-time broadcasting (30 frames per second). Some analyses about the optimization are also included in this paper.
引用
收藏
页码：1606 / 1609
页数：4
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