A Novel Compact and High-Speed CMOS Parity Generator/Checker

During the digital transmission of data, the designer is forced to use one of the various methods of data generation and checking, among them is the parity bit. However, CMOS circuits that generate the parity bit (parity generator) and perform the checking operation (parity checking) usually have wide fan-in and thus have a relatively low speed and high power consumption. In this paper, a novel CMOS scheme is presented for the realization of such functions. The proposed scheme is compared with the conventional static CMOS scheme and other schemes. The proposed scheme is verified by simulation using the 45 nm CMOS technology and shows 80.3% and 60% savings in the power-delay product and the area, respectively, assuming eight bits in a single group of data; however, at the expense of more power consumption and less immunity to process, voltage, and temperature (PVT) variations.