CNTFET Based 4-Trit Hybrid Ternary Adder-Subtractor for low Power & High-Speed Applications

To go through the phenomenon at nanoscale regimes, circuits using the CNTFETbased on Ternary Logic have been explored due to their constantly increasing application in high-speed low power designs. In this paper, 4-Trit Ternary Adder-Subtractor (TAS) using Complementary metal-oxide-semiconductor (CMOS) and Carbon Nanotube Field-Effect Transistor (CNFET) is proposed, which demonstrates the ternary addition and subtraction with a single circuit. The design style is based on conventional static CMOS implementation. The Fundamental ternary logic units are connected to achieve the required design. Therefore, prominence is given to the optimization of these fundamental units. The implementation and simulation are analyzed and validated using Hailey Simulation Program with Integrated Circuit (HSPICE) with PTM low power 32 nm metal gate / High-K / Strained-Si Model for CMOS and 32 nm Stanford Model for CNTFET. The CMOS based design is compared with the CNTFET design in terms of key design factors, namely average delay, power consumption and power delay product(PDP). The simulation results reveal that CNTFET based 4-Trit Ternary Adder-Subtractor accomplishes better results in comparison with CMOS based 4-Trit Ternary Adder-Subtractor design. When compared with CMOS-based 4-Trit TAS, it is found that in CNTFET based 4-Trit TAS the average delay and power consumption is improved by approximately 82% and 71% respectively.