The cost of limit-cycle elimination in IIR digital filters using multiplier blocks

被引:0
作者
Dempster, AG
机构
来源
ISCAS '97 - PROCEEDINGS OF 1997 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I - IV: CIRCUITS AND SYSTEMS IN THE INFORMATION AGE | 1997年
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中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Multiplier blocks significantly reduce tile cost of multiplication in digital filters, especially in structures that allow large numbers of products of a single multiplicand. Some such structures, the direct form and cascaded second-order sections, have previously been shown to be less costly than the wave structure. In this paper, the effects of eliminating zero-input limit-cycles (LC), hereinafter called simply ''limit-cycles'', from these structures is examined. The direct form no longer competes with the wave structure, but the cascade structure is still found to be the most cost-efficient.
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页码:2204 / 2207
页数:4
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