Large Random Telegraph Noise in Sub-Threshold Operation of Nano-Scale nMOSFETs

被引:28
作者
Campbell, J. P. [1 ]
Yu, L. C. [1 ,2 ]
Cheung, K. P. [1 ]
Qin, J. [1 ,3 ]
Suehle, J. S. [1 ]
Oates, A. [4 ]
Sheng, K. [2 ]
机构
[1] NIST, Div Semicond Elect, Gaithersburg, MD 20899 USA
[2] Rutgers State Univ, Dept Elect & Comp Engn, Piscataway, NJ 08855 USA
[3] Univ Maryland, Dept Engn Mech, College Pk, MD 20740 USA
[4] TSMC Ltd, Hsinchu 30077, Taiwan
来源
2009 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUIT DESIGN AND TECHNOLOGY, PROCEEDINGS | 2009年
关键词
RTN; Sub-V-TH operation; SRAM; INTERFACE; MOSFETS; IMPACT; CMOS; AMPLITUDES; DEFECTS; SIGNALS; VOLTAGE;
D O I
10.1109/ICICDT.2009.5166255
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
We utilize low-frequency noise measurements to examine the sub-threshold voltage (sub-V-TH) operation of highly scaled devices. We rind that the sub-V-TH low-frequency noise is dominated by random telegraph noise (RTN). The RTN is exacerbated both by channel dimension scaling and reducing the gate overdrive into the sub-V-TH regime. These large RTN fluctuations greatly impact circuit variability and represent a troubling obstacle that must be solved if sub-V-TH operation is to become a viable solution for low-power applications.
引用
收藏
页码:17 / +
页数:2
相关论文
共 17 条
[1]   RTS amplitudes in decananometer MOSFETs: 3-D Simulation Study [J].
Asenov, A ;
Balasubramaniam, R ;
Brown, AR ;
Davies, JH .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2003, 50 (03) :839-845
[2]   Random telegraph signal amplitudes in sub 100 nm (decanano) MOSFETs: A 3D 'atomistic' simulation study [J].
Asenov, A ;
Balasubramaniam, R ;
Brown, AR ;
Davies, JH ;
Saini, S .
INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, :279-282
[3]   Static noise margin variation for sub-threshold SRAM in 65-nm CMOS [J].
Calhoun, Benton H. ;
Chandrakasan, Anantha P. .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (07) :1673-1679
[4]   A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS [J].
Chang, Ik Joon ;
Kim, Jae-Joon ;
Park, Sang Phill ;
Roy, Kaushik .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (02) :650-658
[5]   Giant random telegraph signals in nanoscale floating-gate devices [J].
Fantini, Paolo ;
Ghetti, Andrea ;
Marinoni, Andrea ;
Ghidini, Gabriella ;
Visconti, Angelo ;
Marmiroli, Andrea .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (12) :1114-1116
[6]   Ultralow-voltage, minimum-energy CMOS [J].
Hanson, S. ;
Zhai, B. ;
Bernstein, K. ;
Blaauw, D. ;
Bryant, A. ;
Chang, L. ;
Das, K. K. ;
Haensch, W. ;
Nowak, E. J. ;
Sylvester, D. M. .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2006, 50 (4-5) :469-490
[7]   Nanometer device scaling in subthreshold logic and SRAM [J].
Hanson, Scott ;
Seok, Mingoo ;
Sylvester, Dennis ;
Blaauw, David .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :175-185
[8]   A UNIFIED MODEL FOR THE FLICKER NOISE IN METAL OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTORS [J].
HUNG, KK ;
KO, PK ;
HU, CM ;
CHENG, YC .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1990, 37 (03) :654-665
[9]   NOISE IN SOLID-STATE MICROSTRUCTURES - A NEW PERSPECTIVE ON INDIVIDUAL DEFECTS, INTERFACE STATES AND LOW-FREQUENCY (1/F) NOISE [J].
KIRTON, MJ ;
UREN, MJ .
ADVANCES IN PHYSICS, 1989, 38 (04) :367-468
[10]   Random telegraph signal in flash memory: Its impact on scaling of multilevel flash memory beyond the 90-nm node [J].
Kurata, Hideaki ;
Otsuga, Kazuo ;
Kotabe, Akira ;
Kajiyama, Shinya ;
Osabe, Taro ;
Sasago, Yoshitaka ;
Narumi, Shunichi ;
Tokami, Kenji ;
Kamohara, Shiro ;
Tsuchiya, Osamu .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (06) :1362-1369