Improvement of Both n- and p-Channel Mobilities in 4H-SiC MOSFETs by High-Temperature N2 Annealing

Effects of high-temperature (1400 degrees C-1600 degrees C) N-2 annealing on the interface states of 4H-SiC/SiO2 and the channel mobility of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) were investigated. It is demonstrated that high-temperature N-2 annealing is effective not only for the reduction of the interface state density near the conduction band edge but also for that near the valence band edge. N-2 annealing improves channel mobility of both n- and p-channel MOSFETs as in the case of nitric oxide (NO) annealing. In particular, the field-effect mobility of the p-channel MOSFETs annealed in an N-2 ambient was improved to 17 cm(2)/Vs, which is 30% higher than that of NO-annealed MOSFETs. The interface state density estimated from the subthreshold slopes in the MOSFETs is much higher than that extracted by the high-low method but is almost comparable to that estimated by the C-psi(s) method in both the cases of interface states near the conduction and the valence band edges. These results suggest that there exist fast states (>1 MHz) near the valence band edge, and these fast states affect the channel mobilities of p-channel SiC MOSFETs as in the case of n-channel MOSFETs.