Optimization and process variation analysis of nano-scale transistors

We utilize fully self-consistent quantum mechanical simulator based on Contact Block Reduction (CBR) method [I] to optimize 10 nm FinFET device to meet ITRS requirements for High Performance (HP) Double-Gate (DG) devices. Fin width, gate oxide thickness, and doping profile are chosen to reflect realistic values and to boost on-current while keeping the total leakage within reasonable limits. We find that the device on-current approaching the value projected by ITRS for HP devices can be obtained using conventional (SI) channel. Our simulation results also show that quantum nature of transport in ultra small devices significantly enhances the intrinsic switching speed of the device. Large and small signal analyses have been performed to extract device capacitances. Sensitivity of device performance to the process variation at room temperature has been investigated.