Analytical dynamic time delay model of strongly coupled RLC interconnect lines dependent on switching

被引:0
|
作者
Shin, S [1 ]
Eo, Y [1 ]
Eisenstadt, WR [1 ]
Shim, J [1 ]
机构
[1] Hanyang Univ, Dept Elect & Comp Engn, Ansan, Kyungki Do, South Korea
关键词
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In today's UDSM(ultra-deep-sub-micron)-process-technology-based ICs, dynamic delay variations of strongly coupled lines (due to neighboring net switching activity) make static timing analysis problematic. In this paper, new analytical timing models for RLC coupled lines are presented and their accuracy is verified. Coupled interconnect lines are decoupled into air effective single line model by rising effective capacitances and effective inductances corresponding to switching activity. Then signal transient waveforms of the effective single line models are determined by exploiting the TWA (Traveling-wave-based Waveform Approximation) technique. This is followed by single line analytical timing model development. It is shown that the models have excellent agreement with SPICE simulations for various circuit performance parameters such as line pitch, line length, driver/receiver size, IMD-thickness, and aspect ratio.
引用
收藏
页码:337 / 342
页数:6
相关论文
共 50 条
  • [1] Delay model for dynamically switching coupled RLC interconnects
    Sharma, Devendra Kumar
    Kaushik, Brajesh Kumar
    Sharma, Rajender Kumar
    EUROPEAN PHYSICAL JOURNAL-APPLIED PHYSICS, 2014, 66 (01):
  • [2] A new analytical delay and noise model for on-chip RLC interconnect
    Cao, Y
    Huang, XJ
    Sylvester, D
    Chang, N
    Hu, CM
    INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST, 2000, : 823 - 826
  • [3] An Analytical Crosstalk and Delay Model for VLSI RLC Coupled Interconnects
    Maheshwari, V.
    Khare, K.
    Jha, S. K.
    Kar, R.
    Manda, D., I
    PROCEEDINGS OF THE 2013 3RD IEEE INTERNATIONAL ADVANCE COMPUTING CONFERENCE (IACC), 2013, : 1568 - 1572
  • [4] An analytical delay model for RLC interconnects
    Kahng, AB
    Muddu, S
    ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 4, 1996, : 237 - 240
  • [5] An analytical delay model for RLC interconnects
    Kahng, AB
    Muddu, S
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (12) : 1507 - 1514
  • [6] Efficient signal integrity verification method of multi-coupled RLC interconnect lines with asynchronous circuit switching
    Je, Taeyong
    Eo, Yungseon
    ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2006, : 419 - +
  • [7] Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles
    Ullah, Muhammad S.
    Chowdhury, Masud H.
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (06) : 1831 - 1841
  • [8] Analysis of RLC Interconnect Delay Model using Second Order Approximation
    Sanaullah, Muhammad
    Chowdhury, Masud H.
    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 2756 - 2759
  • [9] Reducing pessimism in RLC delay estimation using an accurate analytical frequency dependent model for inductance
    Mondal, M
    Massoud, Y
    ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS, 2005, : 691 - 696
  • [10] Compact models for signal transient and crosstalk noise of coupled RLC interconnect lines with ramp inputs
    Kim, Taehoon
    Kim, Dongchul
    Lee, Jung-A
    Eo, Yungseon
    DELTA 2008: FOURTH IEEE INTERNATIONAL SYMPOSIUM ON ELECTRONIC DESIGN, TEST AND APPLICATIONS, PROCEEDINGS, 2008, : 205 - 209