Efficient Implementation of Floating-Point Reciprocator on FPGA

被引：2

作者：

Jaiswal, Manish Kumar ^{[1
]}

Chandrachoodan, Nitin ^{[1
]}

机构：

[1] Indian Inst Technol, Dept Elect Engn, Madras 36, Tamil Nadu, India

来源：

22ND INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH 8TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS | 2009年

关键词：

Floating-point arithmetic; reciprocator; FPGA; double-precision; partial block-multipliers; binomial expansion;

D O I：

10.1109/VLSI.Design.2009.12

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper we have presented an efficient FPGA implementation of a reciprocator for both IEEE single-precision and double-precision floating point numbers. The method is based on the use of look-up tables and partial block multipliers. Compared with previously reported work, the modules occupy less area with a higher performance and less latency. The designs trade off either I unit in last-place (ulp) or 2 ulp of accuracy (for double or single precision respectively), without rounding, to obtain a better implementation. Rounding can also be added to the design to restore some accuracy at a slight cost in area.

引用

页码：267 / 271

页数：5

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